1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device that uses a vertical transistor, and a manufacturing method thereof.
2. Description of Related Art
As for a semiconductor device such as DRAM (Dynamic Random Access Memory), in recent years, as substitutes for conventional planar transistors, research on vertical transistors in which channels are arranged in a vertical direction (or a direction perpendicular to a surface of a semiconductor substrate) has been underway. In the planar transistors, channels are arranged in a lateral direction (horizontal direction). Therefore, the planar transistors have a problem that gate length becomes shorter as the semiconductor devices are miniaturized, and characteristics would deteriorate due to short channel effects. The vertical transistors are intended to solve the problem. That is, since the channels are arranged in the vertical direction, the gate length does not become shorter even as the semiconductor devices are miniaturized. Therefore, compared with the planar transistors, the vertical transistors can obtain excellent characteristics.
In Japanese Patent Application Laid-Opens No. 2008-140996 and No. 2009-081377, a specific example of a semiconductor device having a vertical transistor is disclosed. As disclosed in the Laid-Opens, a vertical transistor includes a semiconductor pillar, which protrudes from a surface of a semiconductor substrate in a vertical direction; a gate insulation film covering a side surface of the semiconductor pillar; a gate electrode covering a surface of the gate insulation film; and an upper diffusion layer provided on an upper surface of the semiconductor pillar; and a lower diffusion layer provided around a bottom surface of the semiconductor pillar.
Also, in recent years, the semiconductor devices such as DRAM have been miniaturized. In case the gate length of transistors used for DRAM is made shorter, short channel effects of the transistors become apparent and a problem that a threshold voltage would drop emerges. And, gathering the impurity concentration of a semiconductor substrate to curb such a decline in the threshold voltage of the transistors causes an increase of junction leakage current. Therefore, miniaturizing of memory cells of the DRAM causes a serious problem that refresh characteristics would deteriorate.
As a structure to avoid such a problem, Japanese Patent Application Laid-Opens No. 2006-339476 and No. 2007-081095 disclose a trench-gate transistor in which a gate electrode is embedded in a trench formed on a surface of a semiconductor substrate. The use of the trench-gate transistor enables to ensure that the gate length of transistors used for DRAM is physically and sufficiently long. Moreover, it enables to realize a DRAM having microscopic memory cells whose minimum feature size is 60 nm or less.
However, as the memory cells of DRAM are further miniaturized, a disturb failure of a trench-gate transistor formed in a memory cell becomes apparent. The explanation of the disturb failure of a transistor in the DRAM (semiconductor device) is given below with reference to FIGS. 99 and 100.
On a surface of a semiconductor substrate 310, a plurality of active regions 330 which are arranged in a regular manner are provided as shown in FIGS. 99 and 100. Each active region 330 is surrounded by an element isolation region 320 which is formed by embedding an insulation film into a trench formed on a surface of the semiconductor substrate 310. In a Y direction (an up-down direction in FIG. 99) that crosses the active regions 330, a plurality of word lines WL1 and WL2 are disposed so as to extend in the Y direction.
As shown in FIG. 99, the word lines WL1 and WL2 are made from a conductive film that is embedded, via a gate insulation film 343, in a trench that is provided on the surface of the semiconductor substrate 310 and across the plurality of active regions 330 and the element isolation region 320. On upper surfaces of the word lines WL1 and WL2, cap insulation films 381 are so formed as to be embedded in trenches. On one active region 330, two word lines WL1 and WL2 cross.
The word lines WL1 and WL2 correspond to transistors Tr1 and Tr2, respectively, and form gate electrodes of the corresponding transistors. The transistors Tr1 and Tr2 are composed of drain diffusion layers 344 and a source diffusion layer 345, in addition to the word lines WL1 and WL2 that function as the gate electrodes. The source diffusion layer 345 is common to the transistors Tr1 and Tr2, and is connected to a bit line 347 through a bit line contact plug 357.
On the other hand, the drain diffusion layers 344 are provided for each of the transistors Tr1 and Tr2. The drain diffusion layer 344 corresponding to the transistor Tr1 is connected to lower electrodes SN1 (a storage node) via one of capacitance contact plugs 346 which are formed in an interlayer insulation film 382. The drain diffusion layer 344 corresponding to the transistor Tr2 is connected to lower electrodes SN2 (a storage node) via another one of capacitance contact plugs 346. Each of the lower electrodes SN1 and SN2 constitutes a capacitance element 390 together with a capacitance insulation film and an upper electrode (not shown). The channel of each of the transistors Tr1 and Tr2 is made in surfaces of the semiconductor substrate 310 corresponding to bottom surfaces and two side surfaces that face each other in the trenches in which the corresponding one of the word lines WL1 and WL2 are embedded.
When the above vertical transistors are also used as cell transistors of the DRAM, a large number of vertical transistors would be densely disposed in a narrow range. The conventional vertical transistors have a structural problem that adjacent gate electrodes become easily short-circuited if the vertical transistors are densely disposed as described above. The problem will be detailed below.
First, a method of manufacturing a vertical transistor that is used as a cell transistor of DRAM will be briefly described with a focus on portions related to the above problem. According to the manufacturing method, first, matrix-pattern semiconductor pillars are formed on a surface of a semiconductor substrate. At this time, a distance between the semiconductor pillars adjacent to each other in a direction of a bit line is made longer than a distance between the semiconductor pillars adjacent to each other in a direction of a word line.
Then, by thermal oxidation, a gate insulation film is formed on a surface of each of the semiconductor pillars. Then, a film of a gate electrode material is formed on the entire surface. The film-forming amount at this time is so adjusted that a film thickness of a gate electrode material formed on a side surface of each of the semiconductor pillars (or a horizontal-direction film thickness) is greater than or equal to one-half of the distance between the semiconductor pillars adjacent to each other in the word-line direction, and is less than one-half of the distance between the semiconductor pillars adjacent to each other in the bit-line direction. Accordingly, two portions of the gate electrode material which are formed on the side surfaces of two of the semiconductor pillars adjacent each other in the word-line direction, respectively, are united, whereas two portions of the gate electrode material which are formed on the side surfaces of two of the semiconductor pillars adjacent each other in the bit-line direction, respectively, are not united. The latter two portions of the gate electrode material are joined by a thin gate electrode material that is formed on a horizontal surface.
In that state, anisotropic dry etching is performed on the gate electrode material. As a result of the etching, only portions of the gate electrode material that are formed on the horizontal surface are removed, and portions of the gate electrode material that are formed on the side surfaces of the semiconductor pillars remain unetched. Therefore, one portion of the gate electrode material formed on the side surface of one of the semiconductor pillars and another one portion of the gate electrode material formed on the side surface of another one of the semiconductor pillars which is adjacent to the one of the semiconductor pillars in the bit-line direction are separated by the etching. Meanwhile, one portion of the gate electrode material formed on the side surface of one of the semiconductor pillars and another one portion of the gate electrode material formed on the side surface of another one of the semiconductor pillars which is adjacent to the one of the semiconductor pillars in the word-line direction are not separated by the etching because they are united. In this manner, a plurality of gate electrodes (word lines) that extend in the word-line direction and are arranged at regular intervals in the bit-line direction are formed. Focusing on one of the semiconductor pillars, gate electrodes are formed on both side surfaces of the bit-line direction. Therefore, the configuration of such gate electrodes are generally referred to as a double gate structure.
In that manner, the gate electrodes of the vertical transistors that are used as cell transistors of DRAM have a double gate structure. And anisotropic dry etching is used in order to separate the portions of the gate electrode material that are formed on side surfaces of two of the semiconductor pillars adjacent to each other in the bit-line direction. If the distance between the semiconductor pillars adjacent to each other in the bit-line direction is sufficiently large, the portions of the gate electrode material are separated without any problem by such a method. However, as the semiconductor devices are further miniaturized, the distance between surfaces of the portions of the gate electrode material that are formed on side surfaces of two of the semiconductor pillars adjacent to each other in the bit-line direction become very short. As a result, even a few errors can cause the portions of the gate electrode material which are formed on the side surfaces of the semiconductor pillars adjacent to each other in the bit-line direction to become united. In this case, the separation cannot be achieved by anisotropic dry etching, and the gate electrodes are short-circuited.
Also, as for the semiconductor device having the configuration as shown in FIGS. 99 and 100, the following problem arises. In a semiconductor device of this type, as shown in FIG. 99, a source diffusion layer 345 needs to be connected to a bit line 347 via a bit line contact plug 357 which is located in a central portion of an active region 330. To that end, the bit line 347 needs to cross the active region 330. In other words, the bit line 347 needs to intersect the active region 330. According to this configuration, the bit line 347 has an overlap in a planar manner with a formation region of a capacitance contact plug 346 to which a capacitance element 390 and a drain diffusion layer 344 are connected.
As a result, since the formation region of the capacitance contact plug 346 becomes smaller, a contact area of each of the lower electrodes SN1 and SN2 and the corresponding one of the capacitance contact plugs 346 decreases. Thus, the contact resistance of each of the lower electrodes SN1 and SN2 and the corresponding one of the capacitance contact plugs 346 increases. This increase of the contact resistance hampers high-speed operation of the semiconductor device (DRAM). The problem becomes more serious as the semiconductor device is further miniaturized.
Further, as described above, the downsizing of the distance between the word lines WL1 and WL2 due to the miniaturization of a semiconductor device such as DRAM causes that electric charges begin to stray because the adjacent word lines WL1 and WL2 are too close to each other, thereby causing a disturb failure.
For example, if the word line WL1 is ON and a channel of the transistor Tr1 is formed, and if a Low (L)-level potential is applied to the bit line 347, the lower electrode SN1 enters an L state. Then, after the word line WL1 is turned OFF, information of L (data “0”) is accumulated in the lower electrode SN1. On the basis of such an operation state, a situation is formed where the L information is accumulated in the lower electrode SN1, and information of His accumulated in the lower electrode SN2. In this situation, a word line WL1 corresponding to the L-side lower electrode SN1 is repeatedly turned ON and OFF (which is equivalent to a cell operation of another active region which uses the same word line WL1).
As a result, electrons e− that are induced in the channel of the transistor Tr1 begin to stray and reach an adjacent drain diffusion layer 344, destroying the H information accumulated in the lower electrode SN2 and turning the H information into the L state. That is, a failure in which data is turned into data “0” occurs. The event probability of the failure depends on the number of times the word lines WL1 is turned ON and OFF. Just as an example, one in a plurality of cells is destroyed while 10,000 times of the operation are repeated, ten in a plurality of cells are destroyed while 100,000 times of the operation are repeated.
Originally, the adjacent cells need to retain information independently. However, if the disturb failure that an accumulation state of one of the cells is destroyed due to an operation state of another one of the cells which is adjacent to the one of the cells occurs, the problem arises that a normal operation of a semiconductor device is hampered, and the reliability thereof is undermined.